1. Field of the Invention
The present invention relates to semiconductor technologies, and more specifically, to a nonvolatile flash memory device and manufacturing method for the same.
2. Description of the Related Art
Flash memory, which is capable of retaining the stored data without continued supply of electrical power, has a stacked gate structure of a floating gate and a control gate. The floating gate, which is placed between the control gate and the semiconductor substrate, is isolated by an insulating oxide layer. When electrons are on the floating gate, they modify the electric field coming from the control gate, which modifies the threshold voltage of the cell. Thus, when the flash memory cell is “read” by applying a specific voltage to the control gate, electrical current will either flow or not flow, depending on the threshold voltage of the cell, which is controlled by the electrons on the floating gate. The presence or absence of current is sensed and translated into 1's and 0's, reproducing the stored data. The flash memory device is classified, according to its cell structure, into two classifications: NOR flash and NAND flash. The NAND flash has higher integration and is suitable for use in electronic devices requiring high storage capacity. The NOR flash memory allows higher speed and random access to the memory cells but it requires a space for the each of memory cells being interconnected to bit line and has relatively low integrity. For increasing the integrity of a cell array, the source regions of NOR memory cells are electrically interconnected in parallel to a word line to form a common source line. With the common source line, a plurality of memory cells have one common contact point, and thus the integrity of a NOR memory cell array can be improved by decreasing the intervals between common contact points.
FIG. 1A is a plan view of the conventional flash memory device and FIGS. 1B to 1D are cross sectional views of FIG. 1A taken along the lines I-I, II-II and III-III, respectively.
Referring to FIGS. 1A to 1D, the conventional flash memory device has an isolation layer 12 for defining active regions in a semiconductor substrate 10, and a plurality of word lines 22 crossing the active regions and the isolation layer 12. Under the word line 22, a stacked structure 22a of a tunnel oxide layer 14, a floating gate 16, a dielectric layer 18 and a control gate 20 is formed. At the sidewalls of the gate stack 22a, spacers 24 are formed. At both sides of the word line 22, source region 26 and drain region 23 are formed. The source region 26 is formed by removing insulating material in the isolation layer 12 and then implanting dopants into the substrate at the isolation layer so that source regions of a plurality of memory cells are interconnected by the source line 26
In the formation of the source line 26, an inclined ion implantation method is used for ensuring the uniform implantation of dopants. In this process, the dopants may be injected into the gate stack 22a, which may degrade the device characteristics. Furthermore, parts of the active region may be recessed during the removal of insulating material in the isolation layer, which may cause accumulated stress at the substrate and an increase of leakage current due to defects in channel regions that neighbor the source line 26.